Memory Block Compiler
Developer: NTLab-systems | all projects
Any IC design automation includes a few approaches and solves different tasks: design time reduction, increase in result predictability, quality and economic issues. One of the tasks for design of ICs which contain large-scale memory blocks (RAM, ROM, EEPROM) is the creation of a software model, netlist and die topology in shortest time. Such a task can be automated by the use of a specially designed software tool ??“ Memory Block Compiler.
The developed compiler has the following features:
- Operates under Windows and Linux OS;
- Automatically performs 6 consequent memory design stages ??“ from functional diagram to technical documentation;
- Generates 9 files of different formats as output including schematics, logic description, topology layout of memory block and additional informative and DRC files;
- Due to optimization algorithms the designed memory blocks have a higher operating speed than compilers created by third-party;
- Typical memory block compilation time is just 0.4 sec. while third-party compiler feature the compilation time ranging from minutes to hours. The hand-made design of a similar memory block would take as much as at least 8 hours by an experienced IC designer.
Resources expended: 36 staff-months
The Customer of the implemented project is a Russian company which accomplishes a series of work within the framework of the federal-level program entitled Development of National Component Base and Radioelectronics.
Programming languages: C++, C#, HTML, VHDL, Verilog, SKILL