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Software Tools Set for IC Design in 0.18 UM Technology

Developer:  NTLab-systems  |  all projects

In practice any IC topology design process is carried out with the employment of standard Computer-Aided Design (CAD) systems on the one hand and with with the help of additional subsidiary software modules on the other one. Those subsidiary software modules bridge the gap between universal design rules which common for all silicon wafer manufacturers and specific requirements of a particular foundry to the design process. Presenting these specific requirements in a standardized form, integration of them into the CAD shell (CAD customization) and automation of checking procedures of design rules - all these tasks were to be solved by project developers. 

The developed Software Tool Set includes: 1) Technological Library Components: - DRC, LVS and PEX layout checking rules for Calibre; - User functions for library integration by the use of DesignArchitect; - Spice models for Eldo; - Netlist generation rules (.ncf). 2) Standard Cell and I/O Cell: - Verilog, VHDL and time models for simulation by the use of Modelsim; - Configurational files for logic synthesis and optimization by the use of Synopsys or LeonardoSpectrum CAD. As a result the Customer received a set of tools which allows design and modeling of ICs with as much predictable results as possible. Such an approach saves hundreds of thousands of US dollars in expenses for a few iterations on IC sampling.

Resources expended: 60 staff-months


The Customer of the implemented Project is a company doing business in semiconductor designing, manufacturing and distribution with its filed offices located in China and HK.

Target area

Programming languages: VHDL, Verilog, SKILL


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